1. Field of the Invention
The invention relates to integrated CMOS light sensing arrays comprising light sensing cells, and in particular to the structure of the light sensing cells.
2. Discussion of the Related Art
CMOS light sensing arrays integrated on chips are widely used in modem imaging devices such as digital cameras or scanners. A light sensing array typically comprises light sensing cells, or pixels, arranged in rows and columns.
FIG. 1 represents a typical light sensing cell of a CMOS light sensing array composed of cells arranged in rows and columns. Such a light sensing cell is for example described in C. Staller et al., “A radiation hard, low background multiplexer design for spacecraft imager applications” in Infrared Readout Electronics, Proc. SPIE, Vol. 1684, pp. 175–181 (1992). The cell comprises a sensor D1, capacitors C1 and C2, and CMOS transistors T1, T2 and T3 of N-channel type. The sensor D1 converts the light received on a sensitive surface into a sensing current Is drawn from a sensing node 2. The capacitor C1 is connected between the sensing node 2 and an output node 4. Output node 4 is connected to a current source 6 supplying a DC supply current I. One single current source 6 is typically connected to all the cells of the same column of the array. The transistor T1 has a gate connected to node 2. The capacitor C2, corresponding to the gate capacitor of transistor T1, is connected between the sensing node 2 and ground GND. The transistor T1 has a source connected to ground and a drain connected to the source of transistor T2. The drain of transistor T2 is connected to the output node 4, and the gate of transistor T2 is connected to a non-illustrated selection block provided for supplying a selection signal SEL. The transistor T3 has its drain connected to the output node 4 and its source connected to the sensing node 2. The gate of transistor T3 is connected to a reset block provided for supplying a reset signal RST.
The cell typically operates as follows. The cell is initially selected by the activation of the selection signal SEL, which closes transistor T2. The cell is then reset by the activation of the signal RST, which closes transistor T3 and short-circuits capacitor C1. After a transitory state, the cell stabilizes in a state where capacitor C1 is discharged and capacitor C2 is charged to a voltage Vrst which depends mainly on I and the threshold voltage of T1. Node 2 then has a stable voltage Vrst, since an increment of the voltage of node 2 increases the current through transistor T1, which discharges node 4 and lowers the voltage of node 2 back to Vrst. In the same way, a decrement of the voltage of node 2 increases the current through transistor T1, so I can charge node 4 and increase the voltage of node 2 back to Vrst.
The reset mode of the cell is then ended (the reset signal RST is inactivated, thus opening the transistor T3) after a given reset time, to enter an acquisition mode. If the sensing current is null, the state of the cell does not change. However, a non-null sensing current Is discharges the capacitor C2, which lowers the gate voltage of transistor T1 and lowers the conductivity of transistor T1. This directs a fraction of the supply current I to the capacitor C1, which charges as a function of the sensing current drawn by the sensor.
Accordingly, the voltage of output node 4 is a function of the sensing current Is drawn by the sensor. A non-illustrated measuring block is provided for measuring the voltage of node 4 a predetermined time (known as the integration time) after the opening of transistor T3. The amount of light received by the sensing cell during the integration time is then determined on the basis of the measured voltage.
A drawback of the above light sensing cell is due to the thermal noise in the transistor T3, which causes capacitor C1 to be charged with a random low parasitic voltage at the opening of transistor T3. If the sensor receives a large quantity of light and supplies a strong sensing current Is, the capacitor C1 charges rapidly and the parasitic voltage is negligible compared to the voltage at the output node. However, if the sensor receives only a small quantity of light and supplies a low sensing current Is, the capacitor C1 charges slowly and the parasitic voltage is no longer negligible compared to the voltage of the output node. The thermal noise therefore considerably lowers the performance of the sensing cell in poorly lit environments.
It is important for a good operation of the sensing cell that capacitor C2 be as small as possible, and that capacitor C1 be as small as possible compared to capacitor C2. However, the smaller the capacitor C1 is, the less the thermal noise is negligible. As an example, for a typical capacitor C2 of 6 fF, a capacitor C1 of 2 fF is preferably used, thus giving rise to a random parasitic voltage that may reach more than 1 mVrms while a typical value of the output node voltage in a poorly lit environment may be only a few 10 mV.
Some known sensing cells solve the above problem by using specific elements such as a photogate inside the sensing cell. However, such elements are not available with typical CMOS processes.
B. Fowler et al., in “Low Noise Readout using active reset for CMOS APS”, Proc. SPIE, Vol. 3965, pp. 126–135, 2000; B. Pain et al., in “Reset Noise Suppression in Two-Dimensional CMOS Photodiode Pixels through Column-based Feedback Reset”, IEDM Technical Digest, pp. 809–812, December 2002 and I. Takayanagi et al., in “A Four Transistor Capacitive Feedback Reset Active Pixel and its Reset Noise Reduction Capability”, 2001 IEEE Workshop on Charge Coupled Devices and Advanced Image Sensors, pp. 118–121, 2001, have each developed specific solutions for suppressing the thermal noise in a CMOS light sensing cell, but none of these solutions is applicable to the pixel type described above.
There is a need for a CMOS sensing cell that is based on the pixel type described above and that is not prone to the above thermal noise problem.